Multi-level nonvolatile semiconductor memory device and...

Details Multi-level nonvolatile semiconductor memory device and... Multi-level nonvolatile semiconductor memory device and...

2007-12-25

2007-12-25

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185180, C365S185200, C365S185240, C365S185230, C365S185250

Reexamination Certificate

active

11416064

ABSTRACT:
A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

REFERENCES:
patent: 6172917 (2001-01-01), Kataoka et al.
patent: 2006/0120152 (2006-06-01), Lee et al.
patent: 11288596 (1999-10-01), None
patent: 2000222894 (2000-08-01), None
patent: 1020010077273 (2001-08-01), None

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