Multi-level non-blocking cache system with inhibiting thrashing

Details Multi-level non-blocking cache system with inhibiting thrashing Multi-level non-blocking cache system with inhibiting thrashing

1997-06-25

2000-11-14

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711140, 711167, G06F 1208

Patent

active

061483710

ABSTRACT:
A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.

REFERENCES:
patent: 4823259 (1989-04-01), Aichelmann, Jr. et al.
patent: 5214765 (1993-05-01), Jensen
patent: 5555392 (1996-09-01), Chaput et al.
patent: 5621896 (1997-04-01), Burgess et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5671444 (1997-09-01), Akkary et al.
patent: 5715428 (1998-02-01), Wang et al.
patent: 5787469 (1998-07-01), Merrell
patent: 5809530 (1998-09-01), Samra et al.
patent: 5867725 (1999-02-01), Fung et al.
Jim Handy, "The Cache Memory Book", pp. 40-46, 1993.
Dileep Bhandarkar and Jason Ding, "Performance Characterization of the Pentium Pro Processor," IEEE, http://iel.ihs.com, 1997.
Smith, Alan Jay; "Cache Memories," Computing Surveys, vol. 14, No. 3, Sep. 1982, pp. 473-530.

Affiliated with

Also associated with

Rating

Multi-level non-blocking cache system with inhibiting thrashing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-level non-blocking cache system with inhibiting thrashing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level non-blocking cache system with inhibiting thrashing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2075781