Multi-level memory devices having memory cell referenced word li

Static information storage and retrieval – Floating gate – Particular biasing

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Details

365210, G11C 1604

Patent

active

061377260

ABSTRACT:
A plurality of memory cell referenced regulators is connected to an output terminal that is configured to connect to a plurality of memory cells of a multi-level memory device. A respective one of the memory cell referenced regulators includes a respective dummy memory cell having a respective predetermined threshold voltage. The plurality of memory cell referenced regulators are responsive to a select signal such that a selected one of the memory cell referenced regulators varies a current at the output terminal to maintain the output terminal at a voltage proportional to the threshold voltage of the dummy memory cell of the selected memory cell referenced regulator. Each of the memory cell referenced regulators may comprise a variable current mirror having a controlled current path and an output current path including the output terminal. The controlled current path includes a controlled impedance therein that provides a variable impedance responsive to a control voltage applied thereto such that current produced at the output terminal is proportional to current in the controlled current path. A control voltage generator is connected between the output terminal and the controlled impedance and includes a dummy memory cell having a predetermined threshold voltage. The control voltage generator is operative to apply a control voltage to the controlled impedance to vary a current at the output terminal when an output voltage at the output terminal is greater than a predetermined voltage proportional to the predetermined threshold voltage of the dummy memory cell.

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