Multi-level memory cell with increased read-out margin

Details Multi-level memory cell with increased read-out margin Multi-level memory cell with increased read-out margin

1991-12-12

1994-03-08

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

For complementary information

365149, 36518901, G11C 700, G11C 1140

Patent

active

052935639

ABSTRACT:
A dynamic semiconductor memory device for storing a signal corresponding to two bits of digital data in a single memory cell. A memory cell consisting of two transistors and one capacitor is formed. Logic is provided to convert two bits of data to two levels of charge with two different polarities. The result is a memory device which requires only 11/2 elements per bit of storage in contrast to the two elements per bit of storage needed in conventional memory cells.

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