Multi-level memory cell

Details Multi-level memory cell Multi-level memory cell

2008-12-16

2011-11-29

Reames, Matthew (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Semiconductor is selenium or tellurium in elemental form

C257SE21002, C257SE29088

Reexamination Certificate

active

08067766

ABSTRACT:
A multi-level memory cell having a bottom electrode, a first dielectric layer, a plurality of memory material layers, a plurality of second dielectric layers, and an upper electrode is provided. The bottom electrode is disposed in a substrate. The first dielectric layer is disposed on the substrate and has an opening exposing the bottom electrode. The memory material layers are stacked on a sidewall of the first dielectric layer exposed by the opening and are electrically connected to the bottom electrode. The second dielectric layers are respectively disposed between every adjacent two memory material layers and are located on the sidewall of the first dielectric layer. The upper electrode is disposed on the memory material layers. A manufacturing method of the multi-level memory cell is further provided. A multi-bit data can be stored in a single memory cell, and both the process complexity and the cost are reduced.

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