Multi-level memory architecture with data prioritization

Details Multi-level memory architecture with data prioritization Multi-level memory architecture with data prioritization

2006-07-13

2009-02-24

Elmore, Reba I (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S206000

Reexamination Certificate

active

07496711

ABSTRACT:
In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.

REFERENCES:
patent: 5592622 (1997-01-01), Isfeld et al.
patent: 5617537 (1997-04-01), Yamada et al.
patent: 2004/0093601 (2004-05-01), Master et al.
patent: 2005/0185463 (2005-08-01), Kanamori et al.
patent: 2006/0230223 (2006-10-01), Kruger et al.

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