Multi-level, low voltage swing sensing scheme for high speed...

Details Multi-level, low voltage swing sensing scheme for high speed... Multi-level, low voltage swing sensing scheme for high speed...

1999-12-22

2002-08-27

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S233100, C365S233500

Reexamination Certificate

active

06442089

ABSTRACT:

BACKGROUND
1. Field
An embodiment of the present invention relates to the field of integrated circuits and, more particularly, to sensing data stored in a memory.
2. Discussion of Related Art
Memory access speed can have a significant impact on processor and/or system performance. For a high-speed microprocessor, for example, an on-chip cache memory that is unable to keep up with the speed of the processor core can slow down the entire processor.
FIG. 1
is a simplified block diagram of a prior cache memory block
100
and corresponding sensing circuitry
105
. The cache memory block
100
of this example is organized into upper and lower blocks
106
and
107
, respectively. To sense selected data stored in the cache memory block
100
in response to a read operation, for example, a sense amplifier (sense amp)
110
is enabled by asserting a sense enable signal received by a sense enable input
112
. D and D# inputs to the sense amplifier
110
are selectively coupled by one of the column multiplexers
115
or
120
to full swing bitlines B and B# corresponding to memory location(s) to be accessed.
Output data from the sensing operation may be provided on one or more of the differential output signal lines O and O# that are coupled to input signal lines D and D#. The sensed data on one or more of the output signals lines O and/or O# is then latched by one or more latches
125
and forwarded over a signal line
130
to requesting circuitry, such as a processor core (not shown). The signal line
130
between the latch
125
and the requesting circuitry may traverse other cache memory blocks and may be relatively long.
An issue may arise when the cache memory that includes the cache memory block
100
is very large and/or an integrated circuit device including the cache memory block
100
operates at a high speed. The time required to sense data from the cache memory and provide it to a processor core or other circuitry may be longer than desired such that the speed of the processor or other devices may be adversely affected.
The slower than desired nature of the sensing operation may be due to the time required for full-swing signals to transition and/or long routing wires that are dominated by resistive-capacitive (RC) delays, particularly for large cache memories, and other factors.
Further, the cache memory block
100
and associated sensing circuitry
105
may consume more power than desired.


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Zhao, Cangsang et al., “An 18-Mb, 12.3-GB/s CMOS Pipeline-Burst Cache SRAM with 1.54 Gb/s/pin,” IEEE Journal of Solid State Circuits, vol. 34, No. 11, Nov. 1999, pp. 1564-1570.

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