Multi-level interrupts

Details Multi-level interrupts Multi-level interrupts

2006-07-18

2006-07-18

Perveen, Rehana (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Handling vector

Reexamination Certificate

active

07080179

ABSTRACT:
Multiple levels of interrupts to be utilized in a computer system, which allows, for example, an interrupt with an interrupt level associated with an application to be distinct from an interrupt with an interrupt level associated with a kernel. The kernel level interrupt may be handled quickly via its own handler, while the application level interrupt may be handled more slowly. This may be accomplished by first determining if a first-level handler is installed for the interrupt source. If so, then it may be called. Otherwise, the interrupt source may be masked and a second-level handler may be called. Once this second-level handler has completed its tasks, the interrupt source may then be unmasked. Implementations with three or more levels of interrupt are also possible.

REFERENCES:
patent: 5828891 (1998-10-01), Benayoun et al.
patent: 6108744 (2000-08-01), Lebee
patent: 6681281 (2004-01-01), Maleck
patent: 6775730 (2004-08-01), Marr et al.
patent: 6820155 (2004-11-01), Ito
patent: 6968411 (2005-11-01), Gaur et al.

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