Multi-level interconnect metallization technique

Details Multi-level interconnect metallization technique Multi-level interconnect metallization technique

1997-12-30

2000-05-30

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438685, 438688, 427531, 427566, 427576, 427597, H01L 2144

Patent

active

06069078&

ABSTRACT:
A method of forming metallization layers and vias as part of an interconnect structure within an integrated circuit ("IC") is disclosed. The metallization layers and vias are formed of an alloy consisting of tungsten and one or more other materials such as aluminum, gold, copper, cobalt, titanium, molybdenum or platinum. In the alternative, the alloy may include aluminum and exclude tungsten. The alloy that forms the metallization layers and vias is deposited onto the IC substrate using ionized cluster beam ("ICB") apparatus. The IC substrate is an "in-process" IC in that various active devices (e.g., bipolar and/or MOS transistors), resistors and capacitors are formed in the substrate using conventional techniques prior to the ICB deposition of the alloy layers. Intermediate IC substrate processing steps (e.g., patterning and etching to form the vias) may take place in-between ICB deposition steps.

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