Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-12-18
1999-01-12
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711125, G06F 1208
Patent
active
058600965
ABSTRACT:
A multi-level instruction cache memory system for a computer processor. A relatively large cache has both instructions and data. The large cache is the primary source of data for the processor. A smaller cache dedicated to instructions is also provided. The smaller cache is the primary source of instructions for the processor. Instructions are copied from the larger cache to the smaller cache during times when the processor is not accessing data in the larger cache. A prefetch buffer transfers instructions from the larger cache to the smaller cache. If a cache miss occurs for the smaller cache, and the instruction is in the prefetch buffer, the system provides the instruction with no delay relative to a fetch from the smaller instruction cache. If a cache miss occurs for the smaller cache, and the instruction is being fetched from the larger cache, or available in the larger cache, the system provides the instruction with minimal delay relative to a fetch from the smaller instruction cache.
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Gleason Craig A.
Knebel Patrick
Undy Stephen R.
Chan Eddie P.
Hewlett--Packard Company
Nguyen Hiep T.
Winfield Augustus W.
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