Multi-level flash memory using triple well

Details Multi-level flash memory using triple well Multi-level flash memory using triple well

1998-03-30

2000-07-18

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 36518501, 438257, 438258, H01L 2994

Patent

active

060911018

ABSTRACT:
A multi-level flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a deep n-well formed in said semiconductor substrate; (b) a p-well formed within said deep n-well; (c) a first insulating layer formed over said p-well; (d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer; (e) source and drain regions formed in said p-well and on either side of said three floating gates; (f) a second insulating layer atop said three floating gates and said drain and source regions; and (g) a control gate formed atop said second insulating layer.

REFERENCES:
patent: 5610419 (1997-03-01), Tanaka
patent: 5751631 (1998-05-01), Liu et al.
patent: 5801415 (1998-09-01), Lee et al.

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