Multi-level encoding/decoding apparatus

Details Multi-level encoding/decoding apparatus Multi-level encoding/decoding apparatus

2007-02-20

2007-02-20

Alavi, Amir (Department: 2624)

Image analysis

Image compression or coding

Pyramid, hierarchy, or tree structure

Reexamination Certificate

active

10464564

ABSTRACT:
A multi-level image encoding/decoding apparatus, which performs bit modeling processing on coefficients, which are the result of wavelet transform of a multi-level image read out from a transform coefficient storage memory, by accessing a significance information memory, a plus/minus sign memory, a processed information memory and a refinement information memory, includes an address generator for generating an address for accessing the processed information memory and the refinement information memory and an address generator for generating an address for accessing the significance information memory and the plus/minus sign memory.

REFERENCES:
patent: 5166956 (1992-11-01), Baltus et al.
patent: 5467132 (1995-11-01), Fazel et al.
patent: 5659579 (1997-08-01), Herzberg
patent: 6651213 (2003-11-01), Hassner et al.
patent: 2004/0213465 (2004-10-01), Nakahara
patent: 2002-101310 (2002-04-01), None
Coefficient bit modeling, Annex C, ISO/IEC CD15444-1 : 1999 (V1.0, Dec. 9, 1999), pp. 69-78.

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