Multi-level DRAM sensing scheme

Details Multi-level DRAM sensing scheme Multi-level DRAM sensing scheme

1998-03-17

1999-06-29

Tran, Andrew Q.

Static information storage and retrieval

Systems using particular element

Ternary

365149, 365203, 365210, G11C 1156

Patent

active

059177489

ABSTRACT:
A multilevel DRAM sensing structure to detect the level of charge and interpret the digital data from a DRAM cell is disclosed. The multi-level sense amplifier structure has a first and second bit line each having a first and second section. A pair of isolation switch transistors separate the first section of the first bit line from the second section of the first bit line. The first section of the second bit line is separated from the second section of the second bit line by a second pair of isolation switch transistors. A latching sense amplifier has a first input connected to one of the pairs of isolation switch transistors, a second input connected to the other pair of isolation switch transistors, and an output connected to external circuitry. The output will have the digital data represented by the charge in the DRAM cell. A cross coupling capacitor is connected between the first section of the first bit line and the second section of the second bit line to couple a charge shift between the first section of the first bit line and the second section of the second bit line to distinguish the low order bit of the digital data. A control logic section is connected to the DRAM cells to control selection of each one DRAM cell, to the latching sense amplifier to control activation of the sense amplifier, and to the isolation switch transistors to control activation and deactivation of the isolation switch transistors.

REFERENCES:
patent: 5532955 (1996-07-01), Gillingham
patent: 5612912 (1997-03-01), Gillingham
patent: 5761114 (1998-06-01), Bertin et al.
T.Murotani et al, "A 4-Level Storage 4GB DRAM", International Solid State Circuit Conf. Digest of Technical Papers. TP 4.6 pp. 74-75, 1997.

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