Multi-level content addressable memory

Details Multi-level content addressable memory Multi-level content addressable memory

2006-05-08

2009-10-20

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S117000

Reexamination Certificate

active

07606968

ABSTRACT:
A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.

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“How To Get Dynamic CAM Entries (CAM Table) for Catalyst Switches Using SNMP,” http://www.cisco.com/warp/public/477/SNMP/cam—snmp.shtml, Cisco Systems Inc., 2003, (downloaded Oct. 5, 2005).
Pagiamtzis, K., “Content-Addressable Memory (CAM) Primer,” http://www.eecg.toronto.edu/˜pagiamt/cam/camintro.html, 2005, (downloaded Oct. 5, 2005).
Liu, H., “Efficient Mapping of Range Classifier into Ternary-CAM,” Stanford University, Aug. 28, 2002.

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