Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-06-19
1998-09-15
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711117, 711118, 711123, 711126, G06F 1208
Patent
active
058095250
ABSTRACT:
A hierarchical cache system comprises first and second pluralities of data caches and first and second respective higher level caches. The first higher level cache is coupled to the first plurality of caches and stores data of the first plurality of caches. The second higher level cache is coupled to the second plurality of caches and stores data of the second plurality of caches. First and second storage controllers access first and second respective address ranges from a main memory and the higher level cache subsystems. The first higher level cache responds to a request for data not contained in the first higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range. The second higher level cache responds to a request for data not contained in the second higher level cache by determining which of the address ranges encompasses the requested data and forwarding the request to the storage controller which can access the determined address range.
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Bishop James Wilson
Carmack, Jr. Charles Embrey
Gallagher Patrick Wayne
Jackowski Stefan Peter
Klouda Gregory Robert
International Business Machines - Corporation
Samodovitz Arthur J.
Swann Tod R.
Thai Tuan V.
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