Multi-level-cell programming methods of non-volatile memories

Details Multi-level-cell programming methods of non-volatile memories Multi-level-cell programming methods of non-volatile memories

2007-02-20

2007-02-20

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200

Reexamination Certificate

active

11281181

ABSTRACT:
The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level 1).

REFERENCES:
patent: 6011725 (2000-01-01), Eitan
patent: 6366496 (2002-04-01), Torelli et al.
patent: 6538923 (2003-03-01), Parker
patent: 6714457 (2004-03-01), Hsu et al.
patent: 7110300 (2006-09-01), Visconti

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