Multi-level cell memory devices and methods using sequential...

Details Multi-level cell memory devices and methods using sequential... Multi-level cell memory devices and methods using sequential...

2008-08-22

2010-10-12

Dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S189160, C365S189050

Reexamination Certificate

active

07813173

ABSTRACT:
An apparatus includes a nonvolatile memory including a plurality of memory cells, each configured to store data having at least two bits and a control circuit configured to write data to a first memory cell connected to a wordline of the nonvolatile memory and to then write data to a second memory cell that is connected to wordline and shares a bit buffer with the first memory cell.

REFERENCES:
patent: 7254064 (2007-08-01), Kim et al.
patent: 7441072 (2008-10-01), Kunori
patent: 2005-285191 (2005-10-01), None
patent: 100206696 (1999-04-01), None
patent: 1020050007653 (2005-01-01), None
patent: 10-2006-0086717 (2006-08-01), None
M. Bauer et al., “A Multilevel-Cell 32 Mb Flash Memory”, 1995 IEEE International Solid-State Circuits Conference, ISSCC Digest of Technical Papers, 7:TA 7.7, pp. 132-133 (Feb. 1995).

Affiliated with

Also associated with

Rating

Multi-level cell memory devices and methods using sequential... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-level cell memory devices and methods using sequential..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level cell memory devices and methods using sequential... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4224331