Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-07-06
2002-02-05
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S690000, C257S692000, C257S693000, C361S760000, C361S764000, C324S755090, C439S071000, C439S074000
Reexamination Certificate
active
06344684
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a multi-layered pin grid array interposer apparatus and method for testing semiconductor devices having non-pin grid array footprints. The present invention has particular applicability in testing semiconductor devices having either a land grid array or a ball grid array footprint.
BACKGROUND ART
In order to test a semiconductor device, such as a microprocessor, the semiconductor device is placed into a socket, e.g., an end user socket, which is connected to a circuit board and the circuit board is connected to a motherboard. As long as the semiconductor device has a pin grid array footprint, the semiconductor device can be placed directly into a pin grid array socket. However, semiconductor devices having non-pin grid array footprints, such as a land grid array or a ball grid array footprint, are becoming increasingly common. Problems arise when these non-pin grid array semiconductor devices need to be tested. Since the circuit boards are configured for pin grid array connections, pin grid array sockets are used for connecting the semiconductor device to the circuit board. Therefore, in order to test a semiconductor device having a non-pin grid array footprint, each connection of the semiconductor device needs to be hard wired to the pin grid array socket. Therefore, there is a need for a pin grid array (PGA) interposer for converting the non-pin grid array footprint of a semiconductor device to a pin grid array footprint, thereby allowing the semiconductor device to be inserted into a pin grid array socket.
Moreover, in order to test semiconductor devices having high pin counts, a multi-layered PGA interposer is needed. However, multi-layered interposers suffer from crosstalk where power and signals on the pins glitch together causing voltage drops and noisy input and output signals which can lead to inaccurate test results. Therefore, there is a need for a multi-layered PGA interposer for testing semiconductor devices having non-pin grid array footprints in which the multi-layered interposer exhibits reduced the crosstalk among the layers.
SUMMARY OF THE INVENTION
The present invention is directed to a multi-layered pin grid array interposer for converting a non-pin grid array footprint of a semiconductor device on a package to a pin grid array footprint. The pin grid array interposer comprises a top signal layer having a plurality of bonding pads on an upper surface, a bottom signal layer having a pin grid array footprint on a bottom surface, at least one power plane between ground layers, the ground layers being between the top signal layer and the bottom signal layer, and a plurality of links for connecting the plurality of bonding pads to a plurality of pins of the pin grid array footprint.
An advantage of the present invention is the testing of semiconductor devices having non-pin grid array footprints. By using a multi-layered PGA interposer to convert the non-pin grid array footprint of a semiconductor device to a pin grid array footprint, the semiconductor device can be tested without requiring each connection to be hard wired, thereby allowing for efficient testing of the semiconductor device having a non-pin grid array footprint.
An additional advantage of the present invention is that the crosstalk between the layers of the multi-layered PGA interposer is reduced since the power plane is between two ground layers. Reducing crosstalk results in accurate test results.
According to the present invention, the foregoing and other advantages are achieved in part by using a multi-layered PGA interposer in which the power layer of the multi-layered PGA interposer is insulated from the signal layers thereby reducing crosstalk among the layers of the multi-layered PGA interposer.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5702255 (1997-12-01), Murphy et al.
patent: 5712768 (1998-01-01), Werther
patent: 5896037 (1999-04-01), Kudla et al.
patent: 6097609 (2000-08-01), Kabadi
patent: 9-320718 (1997-12-01), None
Do Phuc Dinh
Hussain Rafiqul
Tubera Benjamin G.
Advanced Micro Devices , Inc.
Nadav Ori
Thomas Tom
LandOfFree
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