Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-03-07
2002-09-10
Jackson, Jerome (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S723000, C257S724000, C257S784000, C257S777000
Reexamination Certificate
active
06448636
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a multi-layered integrated semiconductor device incorporating a multiplicity of electrically connected integrated circuit (IC) chips.
BACKGROUND OF THE INVENTION
A new type of multi-layered integrated semiconductor devices have been developed which incorporate one IC chip electrically connected to another IC chip.
FIG. 6
shows such a multi-layered integrated semiconductor device as mentioned above.
As seen in
FIG. 6
, a first semiconductor IC chip
610
includes a multiplicity of wiring pads
640
on which protruding electrodes or bumps
650
are formed. A second integrated semiconductor IC chip
620
also includes a multiplicity of wiring pads
660
which face corresponding wiring pads
640
of the first IC chip, on which protruding electrodes or bumps
670
are formed to oppose the bumps
650
. Disposed between the first and the second IC chips
610
and
620
, respectively, is an adhesive anisotropic conductive plastic layer
630
which contains electrically conductive particles dispersed throughout the plastic layer.
The anisotropic conductive layer
630
in contact with the first and the second IC chips
610
and
620
, respectively, is thermocompressed between them. Since portions of the anisotropic conductive layer
630
thus compressed by the bumps
650
and
670
of the first and the second IC chips, respectively, become electrically conductive, electric connections are established between each pair of facing bumps
650
and
670
.
Thus, necessary electric connections can be obtained simultaneously for the wiring pads of the first and the second IC chips.
The multi-layered integrated IC device
600
of the first and the second semiconductor IC chips
610
and
620
is then wire bonded, by means of wires W, to the wiring pads
680
and external lead terminals T formed on the periphery of the second IC chip
620
, followed by encapsulation by a plastic, thereby forming a single package of the multi-layered integrated IC chips.
Advantageously, this integration technique, often called chip-on-chip technique, requires no wire bonding in packaging two IC chips into a multi-layered integrated IC device
600
, so that it can be done quickly and permit minimization of the integrated IC device.
However, in such multi-layered integrated IC devices integrated by chip-on-chip technique, wiring pads (including the bumps thereof if used) of the upper or first IC chip
610
are connected to the associated wiring pads of the lower or second IC chip
620
, and electrically connected to external terminals T through internal gates of the second IC chip
620
.
Consequently, it is impossible to measure pad-to-pad resistances between the corresponding wiring pads of the upper and the lower IC chips
610
and
620
, respectively. As a result, quality tests to remove faulty products is difficult to do, and so is provision of a guarantee for the products.
SUMMARY OF THE INVENTION
The invention is directed to a multi-layered integrated semiconductor IC device incorporating a first and a second IC chips connected with each other via a first and a second sets of wiring pads of the first and the second IC chip, respectively, such that pad-to-pad resistances between the associated wiring pads can be externally measured by means of an external measurement device, thereby increasing the reliability of the wiring pad connections.
In one aspect of the invention, there is provided a multi-layered integrated semiconductor device incorporating a first and a second IC chips which are connected with each other via a first set of wiring pads of the first IC chip to a second set of wiring pads of the second IC chip each formed in opposition to a corresponding wiring pad of the first IC chip, the integrated semiconductor device comprising:
a first set of distributed monitoring pads formed on said first IC chip, said monitoring pads connected in pairs;
a second set of monitoring pads each formed on the second IC chip, in opposition to an associated one of said first monitoring pads; and
a multiplicity of external monitoring terminals each formed on said semiconductor device and connected to an associated one of said second monitoring pads,
thereby allowing measurements of pad-to-pad resistances between corresponding monitoring pads of said first and second IC chips using an associated pair of said external monitoring terminals connected to said corresponding pads.
Since the integrated chip has a feature that the pad-to-pad resistances between the wiring pads of the first and the second semiconductor IC chips can be measured directly via the external terminals, they can be tested and removed if it has a faulty connection even after the upper and the lower IC chips are integrated, thereby providing a greater reliability of the products.
The pair-wise connected first monitoring pads are preferably formed at the periphery of the first IC chip, so that the wiring pads may be securely formed well on the monitoring pads and have less resistances than the pad-to-pad resistances of the monitoring pads.
The pair-wise connected first monitoring pads may alternatively be disposed at the four corners of the first IC chip.
In this case, the pad-to-pad resistance of a given pair of the wiring pads of the first and the second IC chips can be obtained accurately from the measurements using the four-cornered terminals, because the measured values are proportional to the distances from the four-cornered terminals to the pair. Since the integrated semiconductor device is materially hard and non-deformable, such measurement of pad-to-pad resistances of the wiring pads will not be appreciably affected by the deformation if the measurements are performed at the four corners.
It would be understood that one of the pair-wise connected monitoring pads may substitute for the associated wiring pad of the first IC chip, thereby reducing the number and cost of the monitoring pads and external monitoring terminals for the monitoring pads.
In another aspect of the invention, there is provided a multi-layered integrated semiconductor device incorporating a first and a second IC chips which are connected with each other, said integrated semiconductor device comprising:
a first power supply pad formed on said first IC chip and connected to a power supply line;
a first grounding pad formed on said first IC chip and connected to a ground line;
a first set of wiring pads formed on said first IC chip and connected via diodes to said power supply line. and ground line and said first IC chip;
a second power supply pad formed on said second IC chip in opposition to said first power supply pad;
a second grounding pad formed on said second IC chip in opposition to said first grounding pad;
a second set of wiring pads formed on said second IC chip, in opposition to the respective wiring pads of said first IC chip;
a multiplicity of switchable connection circuits formed on said second IC chip for selectively connecting said second wiring pads to either said second IC chip or an external test signal line;
an external power supply pad connected to said second power supply pad;
an external grounding terminal connected to said second grounding pad; and
a multiplicity of external test terminals connectable to said external test signal line.
This arrangement enables measurement of pad-to-pad resistances of the first and second wiring pads by means of the external test terminals, the power supply terminals, and the grounding terminals.
That is, a pad-to-pad resistance of a particular pair of the first and second wiring pad of interest can be directly measured using the power supply terminal connected to the test terminal or power supply pad, and the grounding pad connected to the wiring pad, by selectively connecting an appropriate test terminal to the wiring pad of the second IC chip by means of the switchable connection circuits. Such measurements enables detection and elimination of faulty products to guarantee required quality of the products.
It should be noted that no structural modification or addition of
Kishino Tatsuo
Suenaga Yoshiaki
Cruz Lourdes
Hogan & Hartson LLP
Jackson Jerome
Rohm & Co., Ltd.
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