Multi layer thin film wiring process featuring self-alignment of

Details Multi layer thin film wiring process featuring self-alignment of Multi layer thin film wiring process featuring self-alignment of

1990-04-26

1992-07-14

Bowers, Jr., Charles L.

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

430313, 430315, 430319, 430327, 430328, 430329, 430394, 430945, 156643, 156656, 1566591, 1566611, G03C 500, G03C 558, G03F 730

Patent

active

051302292

ABSTRACT:
The present invention provides a packaging semiconductor structure and method for obtaining same. The structure is comprised of at least one level of dielectric and metallurgy layers. The at least one level is comprised of a wiring metallurgy plane and a "through-via" plane of interconnecting metallurgy in association with both one and two layers of polymeric dielectric materials. The self-alignment method of fabrication of the level provides a streamlined technique wherein stringent masking and alignment requirements are relaxed, undue processing such as at least one polishing step is eliminated and a structure having adhesive integrity is fabricated.

REFERENCES:
patent: 4307179 (1981-12-01), Chang et al.
patent: 4702792 (1987-10-01), Chow et al.
patent: 4774127 (1988-09-01), Reagan et al.
patent: 4786569 (1988-11-01), Rohde et al.
IBM Technical Disclosure Bulletin, vol. 19, No. 3, 1976 by S. E. Greer, pp. 911-912.
Ohsaki, et al., "A Fine-Line Multilayer Substrate with Photo-sensitive Polymide Dielectric and Electroless Copper Plated Conductors", Third IEEE/CHMT International Electronic Manufacturing Technology Symposium, pp. 178-183, Oct. 12-14, 1987.
English language abstract of European Patent Application 0286854, published Apr. 1987.

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