Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With stress relief
Reexamination Certificate
2005-11-15
2005-11-15
Thai, Luan (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With stress relief
C257S642000, C257S643000, C257S674000
Reexamination Certificate
active
06965158
ABSTRACT:
Multi-layer components such as circuit panels are fabricated by connecting conductive features such as traces one two or more superposed substrates using leads extending through an intermediate dielectric layer. The leads can be closely spaced to provide a high density vertical interconnection, and can be selectively connected to provide customization of the structure.
REFERENCES:
patent: 3577037 (1971-05-01), Di Pietro
patent: 3795037 (1974-03-01), Luttmer
patent: 3811186 (1974-05-01), Larnerd et al.
patent: 3842187 (1974-10-01), Barkan
patent: 3921285 (1975-11-01), Krall
patent: 3952404 (1976-04-01), Matunami
patent: 4402562 (1983-09-01), Sado
patent: 4520562 (1985-06-01), Sado et al.
patent: 4535219 (1985-08-01), Sliwa, Jr.
patent: 4563725 (1986-01-01), Kirby
patent: 4629957 (1986-12-01), Walteis et al.
patent: 4764848 (1988-08-01), Simpson
patent: 4785137 (1988-11-01), Samuels
patent: 4793814 (1988-12-01), Zifcak et al.
patent: 4893172 (1990-01-01), Matsumoto et al.
patent: 4926241 (1990-05-01), Carey
patent: 4937653 (1990-06-01), Blonder et al.
patent: 4949158 (1990-08-01), Ueda
patent: 4954877 (1990-09-01), Nakanishi et al.
patent: 4954878 (1990-09-01), Fox et al.
patent: 4970577 (1990-11-01), Ogihara et al.
patent: 5047830 (1991-09-01), Grabbe
patent: 5067007 (1991-11-01), Kanji et al.
patent: 5086337 (1992-02-01), Noro et al.
patent: 5131851 (1992-07-01), Grabbe et al.
patent: 5152695 (1992-10-01), Grabbe et al.
patent: 5173055 (1992-12-01), Grabbe
patent: 5189507 (1993-02-01), Carlomagno et al.
patent: 5197892 (1993-03-01), Yoshizawa et al.
patent: 5282312 (1994-02-01), DiStefano et al.
patent: 5367764 (1994-11-01), DiStefano et al.
patent: 5385291 (1995-01-01), Latta
patent: 5430614 (1995-07-01), Difrancesco
patent: RE35119 (1995-12-01), Blonder et al.
patent: 5518964 (1996-05-01), DiStefano
patent: 5587341 (1996-12-01), Masayuki et al.
patent: 5637925 (1997-06-01), Ludden et al.
patent: 5684677 (1997-11-01), Uchida et al.
patent: 5726500 (1998-03-01), Duboz et al.
patent: 5739053 (1998-04-01), Kawakita et al.
patent: 5763941 (1998-06-01), Fjelstad
patent: 5794330 (1998-08-01), Distefano et al.
patent: 5801441 (1998-09-01), DiStefano
patent: 5830782 (1998-11-01), Smith et al.
patent: 5859472 (1999-01-01), DiStefano et al.
patent: 5898223 (1999-04-01), Frye et al.
patent: 6016013 (2000-01-01), Baba
patent: 6057598 (2000-05-01), Payne et al.
patent: 2001/0002624 (2001-06-01), Khandros et al.
patent: 596393 (1994-05-01), None
patent: WO 97/11588 (1997-03-01), None
patent: WO 98/44564 (1998-10-01), None
Haba Belgacem
Smith John W.
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
Thai Luan
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