Multi-layer structure for reducing capacitance and...

Details Multi-layer structure for reducing capacitance and... Multi-layer structure for reducing capacitance and...

2002-08-21

2003-09-23

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

C438S669000, C438S670000, C438S719000

Reexamination Certificate

active

06624054

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to and claims all benefits accruing under 35 U.S.C. Section 119 from an application entitled, “MULTI-LAYER STRUCTURE FOR REDUCTION OF CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME,” filed in the Korean Intellectual Property Office on Mar. 5, 2002 and there duly assigned Serial No. 2002-11495.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer structure for reducing capacitance and a manufacturing method thereof, in particular, for reducing capacitance between metal patterns of a Silicon Optical Bench (SiOB), which is used in optical communication applications.
2. Description of the Related Art
As one skilled in the art can appreciate, a laser-diode chip and a photo-diode chip are used as a Transceiver (Tx) and a Receiver (Rx) of optical subscriber elements, respectively, in which a Silicon Optical Bench (SiOB) is deployed to connect these chips as a single module. In manufacturing this type of SiOB, the magnitude of capacitance plays an important role as the capacitance is enlarged and the frequency performance is degraded, thereby preventing the module from performing at high speed.
FIG. 1
is a sectional view illustrating a bench structure used for manufacturing an optical bench, such as SiOB, in which a SiN or SiO
2
dielectric film
2
, and metal patterns
4
and
4
′ are formed on a silicon substrate
1
.
FIG. 2
illustrates a circuit diagram equivalent to
FIG. 1
, in which a section marked by a circle, i.e., a capacitance CS, an inductance LS, or a resistance RS, between the metal patterns
4
and
4
′, represents similar components served by the dielectric film and the silicon substrate between the metal patterns. Note that this type of structure increases the capacitance.
In order to reduce the capacitance between the metal patterns
4
and
4
′ in the above conventional structure, the resistance of silicon is raised, the thickness of the dielectric film is increased, and the area of the metal patterns is reduced.
However, the first method of raising the resistance of silicon requires cost increase due to delicate techniques in a silicon-wafer fabricating process. In the second method of thickening the dielectric film, the desired thickness of deposition is hard to obtain due to the limited Chemical Vapor Deposition (CVD), such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD). Although the thickness can be increased if the thermal-oxidation deposition technique is employed in the second method, the deposition time is undesirably long. Lastly, the third method of reducing the area of the metal patterns has drawbacks with a limit on how much to decrease the metal pattern area due to physical and structural constraints.
SUMMARY OF THE INVENTION
Accordingly, the present invention overcomes the above-described problems and provides additional advantages, by providing a manufacturing method and a multi-layer structure for reducing capacitance, in which the capacitance can be effectively reduced without changing the area or structure of metal patterns.
According to one aspect of the invention, the multi-layer structure includes a dielectric layer and conductive patterns on a semiconductor substrate, wherein the conductive patterns are separated from each other, and wherein the dielectric layer and upper portions of the semiconductor substrate between the conductive patterns are etched out to a predetermined thickness.
Preferably, the etched-out portions of the silicon substrate between the conductive patterns have a thickness of 0.5-2 &mgr;m.
Preferably, the dielectric layer is a SiO
2
layer.
According to another aspect of the invention, a method of manufacturing a multi-layer structure is provided, as well, as a method comprising the following steps: (a) forming a dielectric layer on a silicon substrate; (b) forming metal patterns separate from each other on the dielectric layer to expose portions of the dielectric layer underlying the metal patterns; and, (c) etching the exposed portions of the dielectric layer and upper portions of the underlying silicon substrate between the metal patterns to a predetermined thickness.
Preferably, the (b) step comprises the steps of carrying out lift-off photolithography to form lift-off photo-sensitive patterns on the dielectric layer except for areas for forming the metal patterns; depositing metal over the entire structure; and, removing the photosensitive patterns and metal deposited on the photosensitive patterns via a lift-off process to form metal patterns.
Preferably, the (c) step of etching the exposed portions of the dielectric layer and upper portions of the underlying silicon substrate between the metal patterns for a certain thickness comprises the step of dry-etching the exposed underlying dielectric layer and subsequently over-etching to remove the upper portions of the underlying silicon substrate by using the metal patterns as an etching mask.


REFERENCES:
patent: 5001085 (1991-03-01), Cathey et al.
patent: 5053105 (1991-10-01), Fox, III
patent: 6156485 (2000-12-01), Tang et al.
patent: 6268287 (2001-07-01), Young et al.
Wolf, S., et al., Silicon Processing for the VLSI Era, vol. 1, 1986, Lattice Press, pp. 534-536.

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