Multi-layer stacked wafer level semiconductor package module

Details Multi-layer stacked wafer level semiconductor package module Multi-layer stacked wafer level semiconductor package module

2008-03-14

2010-12-28

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257S686000, C257SE23101

Reexamination Certificate

active

07859102

ABSTRACT:
A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.

REFERENCES:
patent: 6750545 (2004-06-01), Lee et al.
patent: 2005/0194674 (2005-09-01), Thomas et al.
patent: 1020010055041 (2001-07-01), None
patent: 100650763 (2006-11-01), None

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