Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2011-08-09
2011-08-09
Williams, Alexander O (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257SE23141, C257SE23023, C257SE25013, C257SE25023, C257SE21502, C257SE21499, C257SE21575, C257S692000, C257S777000, C257S723000, C257S784000, C257S778000, C257S738000, C257S737000
Reexamination Certificate
active
07994626
ABSTRACT:
A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package.
REFERENCES:
patent: 6339254 (2002-01-01), Venkateshwaran et al.
patent: 6558978 (2003-05-01), McCormick
patent: 6774478 (2004-08-01), Eto et al.
patent: 6828665 (2004-12-01), Pu et al.
patent: 6838761 (2005-01-01), Karnezos
patent: 6861288 (2005-03-01), Shim et al.
patent: 7061088 (2006-06-01), Karnezos
patent: 7180165 (2007-02-01), Ellsberry et al.
patent: 7429786 (2008-09-01), Karnezos et al.
patent: 7608921 (2009-10-01), Pendse
patent: 2002/0113308 (2002-08-01), Huang et al.
patent: 2003/0137041 (2003-07-01), Blackshear et al.
patent: 2004/0036164 (2004-02-01), Koike et al.
patent: 2004/0089943 (2004-05-01), Kirigaya et al.
patent: 2005/0012195 (2005-01-01), Go et al.
patent: 2006/0110849 (2006-05-01), Lee et al.
patent: 2007/0181990 (2007-08-01), Huang et al.
patent: 2007/0210433 (2007-09-01), Subraya et al.
patent: 2007/0254404 (2007-11-01), Gerber et al.
patent: 2008/0017966 (2008-01-01), Williams et al.
patent: 2008/0029869 (2008-02-01), Kwon et al.
patent: 2008/0042250 (2008-02-01), Wilson et al.
patent: 2008/0057624 (2008-03-01), Lee
patent: 2008/0136007 (2008-06-01), Kim et al.
patent: 2008/0150115 (2008-06-01), Watanabe et al.
Pendse et al., “Bond-on-Lead: A Novel Flip Chip Interconnection Technology for Fine Effective Pitch and High I/O Density”, 2006 Electronic Components and Technology Conference, May 30-Jun. 2, 2006.
Dr. Rajendra D. Pendse, “Future Directions in Package-level Integration” APIA Symposium, Jul. 15, 2004, 18 pages.
“Data Sheet—Package Stackable Very Thin Fine Pitch BGA (PSvfBGA)”, Amkor Technology, Apr. 2006, 2 pages.
Roger Allan, “SiP Really Packs It in”, Electronic Design, Nov. 29, 2004, 13 pages, http://www.elecdesign.com/Articles/Print.cfm?ArticleID-9175.
Mario Aguirre, “Super High Density Packaging Technologies”, Fujitsu Microelectronics America, Inc., Sep. 2002, 23 pages.
“Data Sheet—Stacked CSP (S-CSP)”, Amkor Technology, Jul. 2005, 2 pages.
Stats Chippac, Inc.
Williams Alexander O
LandOfFree
Multi-layer semiconductor package with vertical connectors... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-layer semiconductor package with vertical connectors..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-layer semiconductor package with vertical connectors... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2778702