Multi-layer interconnection layout between a chip core and perip

Details Multi-layer interconnection layout between a chip core and perip Multi-layer interconnection layout between a chip core and perip

1998-09-11

2000-12-12

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

438617, 438622, 438666, H01L 2144, H01L 2148, H01L 2150

Patent

active

061597740

ABSTRACT:
An integrated circuit chip has a multi-layer input/output pad interconnection structure which allows input/output buffers to be flexibly coupled to input/output pads depending on the chip's applications. To obtain the multi-layer pad interconnection structure, a first interconnection layer is formed on a layer of a semiconductor wafer such that the first interconnection layer is electrically coupled to the input/output buffers. The first interconnection layer is patterned into the first interconnection lines. An insulating layer is formed on the first interconnection layer. A second interconnection layer is formed on the insulating layer such that the second interconnection layer is electrically coupled to the input/output pads and the first interconnection lines. The first interconnection lines and the second interconnection layer are electrically coupled to each other via contacts. The second interconnection layer is then patterned into a plurality of second interconnection lines.

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