Multi-layer interconnect with isolation layer

Details Multi-layer interconnect with isolation layer Multi-layer interconnect with isolation layer

2008-05-20

2008-05-20

Goudreau, George A. (Department: 1792)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S239000, C438S694000, C430S005000

Reexamination Certificate

active

10713845

ABSTRACT:
An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.

REFERENCES:
patent: 3991231 (1976-11-01), Trausch
patent: 4546534 (1985-10-01), Nicholas
patent: 4675981 (1987-06-01), Naruke
patent: 5057888 (1991-10-01), Fazan et al.
patent: 5250457 (1993-10-01), Dennison
patent: 5292677 (1994-03-01), Dennison
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5401681 (1995-03-01), Dennison et al.
patent: 5488011 (1996-01-01), Figura et al.
patent: 5554557 (1996-09-01), Koh
patent: 5940714 (1999-08-01), Lee et al.
patent: 5981149 (1999-11-01), Yamaguchi
patent: 5998257 (1999-12-01), Lane et al.
patent: 6046093 (2000-04-01), DeBoer et al.
patent: 6083803 (2000-07-01), Fischer et al.
patent: 6083831 (2000-07-01), Dennison
patent: 6174767 (2001-01-01), Chi
patent: 6184079 (2001-02-01), Lee
patent: 6204143 (2001-03-01), Roberts et al.
patent: 6221711 (2001-04-01), Roberts et al.
patent: 6222222 (2001-04-01), DeBoer et al.
patent: 6251710 (2001-06-01), Radens et al.
patent: 6258490 (2001-07-01), Bula et al.
patent: 6365453 (2002-04-01), Deboer et al.
patent: 6417065 (2002-07-01), Wu et al.
patent: 08-167580 (1996-06-01), None
Sakao et al., “A Capacitor-Over-Bit-Line (COB) Cell with Hemispherical-Grain Storage Node for 64Mb DRAMs,”IEDM, vol. 90, San Francisco Dec. 9, 1990-Dec. 12, 1990, pp. 27.3.1-27.3.4.

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