Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-08-24
2002-08-27
Utech, Benjamin L. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S723000, C438S724000
Reexamination Certificate
active
06440858
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of semiconductor manufacture, and more specifically to the formation of deep trenches when etching silicon.
This invention describes a process for etching multiple films with a dual layer hard mask, and specifically a process for etching deep trenches for DRAMs having a dual layer hard mask. The top hard mask is totally and the lower hard mask is partially removed while etching the deep trench.
2. Description of Related Art
In the formation of integrated circuits, it is often necessary to etch a trench in the silicon substrate. In particular, the trend towards packing more memory cells into a given chip area has led to the development of trench memory cells which require deep, narrow apertures in the silicon substrate. Trench memory cells and trench capacitors with one or more polysilicon electrodes for silicon integrated circuits have applications in structures known as dynamic random access memories (DRAMs).
Deep trench etching of the silicon substrate has many problems during the etching process and in the post-etch processing of the substrate. The side walls of trench cells and trench capacitors must be substantially vertical to minimize the amount of space consumed by the trench. However, the manufacturing sensitivity of the silicon substrate can inhibit control and precision during the etching process. In post-etch processing, hard masks used in patterning the trenches must be removed with minimal undercutting of the pad dielectric on the substrate. In addition, manufacturing costs are driven up when there are multiple masking steps, and seasoning changes in the etch tool.
U.S. Pat. No. 4,717,448 (issued Jan. 5, 1988, to Cox et al. and assigned to the assignee of the present invention), discloses a process for forming deep trenches in a silicon substrate having a layer of silicon oxide, and a photoresist layer. Undercutting of the silicon oxide can occur during deep trench etching of the substrate utilizing this method.
U.S. Pat. No. 4,983,253 (issued Jan. 8, 1991, to Wolfe et al.) discloses an apparatus and method of etching a silicon wafer having a layer of pad oxide wherein two masking layers may be used when etching the silicon. This method requires additional steps to remove the masking layers.
U.S. Pat. No. 5,275,974 (issued Jan. 4, 1994, to Ellul et al.), discloses a method of forming trench capacitor electrodes with reduced masking steps by etching a substrate coated, first, with a layer of silicon nitride as a chemical mechanical polish stop and then coated with a layer of silicon oxide to serve as a trench etch mask. The silicon oxide is removed during post-etch processing and later re-grown.
U.S. Pat. No. 5,470,782 (issued Nov. 28, 1995, to Schwalke et al.), discloses a method for producing trench structures in silicon substrates using a two-stage trench process comprising at least two etching steps utilizing multiple layers of silicon dioxide, mono- and polycrystalline silicon, and silicon nitride. The layers are etched first followed by etching of the silicon substrate. This method involves several time consuming deposition steps.
DRAMs have been manufactured with a borosilicate glass (BSG)/pad nitride hard mask and with a tetraethylorthosilicate (TEOS)/pad nitride hard mask. Following deep trench etch of the TEOS/pad nitride product, the same chamber is often used to run BSG/pad nitride product. The chamber experiences process shifts causing the BSG product to etch deeper, and erode the BSG/pad nitride hard mask. A current solution to this problem is to allow a buildup of BSG products before seasoning the chamber from the TEOS product run. After running the BSG product, the chamber must be reseasoned to prepare the chamber for running TEOS products. Dedicating chambers based on tool, process, or product differences is not a manufacturable solution since it impacts capacity. A more flexible manufacturing solution is desirable.
Bearing in mind the problems and deficiencies of the prior art, it is an object of the present invention to provide a method of deep trench etching silicon having improved control and precision to allow etching trenches of close proximity and/or with multiple dimensions and directions.
Another object of the present invention is to provide a method of deep trench etching silicon having reduced pad oxide undercut.
It is yet another object of the present invention to provide a method of deep trench etching silicon having improved post-etch processing.
A further object of the present invention is to provide a silicon substrate for etching a plurality of trenches within close proximity.
A still further object of the present invention is to provide a silicon substrate for etching a plurality of trenches having multiple dimensions and directions.
Yet another object of the present invention is to provide an improved manufacturing process for deep trench etching of DRAMs.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of etching a plurality of trenches in a semiconductor substrate. The method comprises the steps of: (a) providing a semiconductor substrate capable of being etched with a first etchant, having a layer of pad dielectric disposed thereon; (b) depositing a layer of material capable of selective removability with respect to the pad dielectric; (c) depositing a layer of material having a slower etch rate than the semiconductor substrate and the layer of material capable of selective removability with respect to the pad dielectric when contacted with the first etchant; (d) patterning at least one of the layers to form a pattern for the trench; (e) etching through the layers; and (f) contacting the semiconductor substrate with the first etchant to form the trench and removing the layer of material having a slower etch rate than the semiconductor substrate.
Preferably, in step (b) the layer of material capable of selective removability with respect to the pad dielectric is borosilicate glass (BSG). Preferably, in step (c) the layer of material having a slower etch rate than the semiconductor substrate when contacted with the first etchant is a layer of silicon oxide deposited by plasma enhanced chemical vapor deposition.
Preferably, during step (e) etching of the pad dielectric, the layer of material capable of selective removability with respect to the pad dielectric, and the layer of material having a slower etch rate than the semiconductor substrate, there is no substantial etching of the semiconductor substrate.
Preferably, etching of the silicon substrate comprises reactive ion etching with an etchant comprising hydrogen bromide gas, nitrogen triflouride, with oxygen and helium. Most preferably, during etching of the silicon substrate, the nitrogen triflouride completely removes the layer of silicon oxide.
Preferably, further including in step (f) removing any remaining layer of material capable of selective removability with respect to the pad dielectric, and removing the layer of material having a slower etch rate than the semiconductor substrate when contacted with the first etchant comprising dipping the semiconductor substrate in a hydrogen fluoride-sulfuric acid bath selective to the layer of pad dielectric and the silicon substrate.
A first preferred sequence of the first three steps is: first, providing a semiconductor substrate capable of being etched with a first etchant, having a layer of pad dielectric disposed thereon; followed by depositing a layer of material capable of selective removability with respect to the pad dielectric; then depositing a layer of material having a slower etch rate than the semiconductor substrate and the layer of material capable of selective removability with respect to the pad dielectric when contacted by the first etc
Canale Anthony J.
Cronin John E.
DeLio & Peterson LLC
International Business Machines - Corporation
Reynolds Kelly M.
Sabo William D.
Umez-Eronini Lynette T.
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