Multi-layer film stack polish stop

Details Multi-layer film stack polish stop Multi-layer film stack polish stop

2002-02-05

2004-11-09

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C438S693000, C438S700000, C438S737000

Reexamination Certificate

active

06815353

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to shallow trench isolation of semiconductor devices, and more particularly to a process for improved dielectric polish control in the fabrication of devices using shallow trench isolation.
BACKGROUND
Shallow trench isolation (STI) is a process used to isolate or separate active regions of devices in an integrated circuit from one another. STI may be used to isolate active device regions in MOS structures, as well as bipolar structures. A conventional STI process includes etching a trench between active device regions and filling the trench with a dielectric, usually silicon dioxide. Following deposition of the dielectric, an STI polish using a nitride polish stop layer is typically performed to remove oxide from the active device regions.
STI provides many advantages when fabricating bipolar devices. For example, STI can reduce peripheral junction capacitance with nearly planar junction breakdown and a nearly planar surface. However, one of the difficulties in using STI with bipolar devices is that the active device regions are small compared to the size of the trenches. These small active device regions may be over-polished during the extensive polishing that occurs during a conventional STI oxide polish step. Additionally, smaller active device regions are over-polished to a greater extent than larger active device regions, which leads to different oxide step heights at the edge of the active device regions. For example, the oxide step height at the edge of a smaller active device region may be as small as 0 angstroms (no step), while the oxide step height at the edge of a larger active device region may be as large as about 2000 angstroms.
This oxide step height variation can have negative effects on some semiconductor devices. For example, in a field oxide walled emitter NPN device, the variation in oxide step height may cause collector-to-emitter shorts by blocking the base implant, as well as n
+
polysilicon stringers along the oxide step for polysilicon emitter structures. The collector to emitter shorts are especially problematic when using very shallow base off-axis implants, which can be blocked entirely by the oxide wall edge.
A number of methods have been developed to minimize over-polishing the active device regions. Dummy active areas can be added to provide a larger polish stop area, but are not practical for dense layouts. Highly selective polishing methods have been used for the STI polish, in order to reduce the amount of overpolishing. However, highly selective polishing methods may not provide acceptable oxide step height uniformity. Pre-planarization techniques, which include resist planarization, dummy resist planarization, and reverse STI mask with isotropic or anisotropic etch, provide more uniform polishing. However, they require extra processing steps, increasing the cost and complexity of wafer processing. Furthermore, they are difficult to control, since they depend on the difference between the STI etch depth and oxide deposition thickness.
In resist planarization, a blanket layer of resist is spun-on to the surface over the oxide, forming a substantially planar surface. Since the surface is substantially planar, the resist is thinner over regions where the oxide layer is thicker; that is, the active device regions. The resist and oxide are then thinned by etching with nearly equal selectivities by plasma etching techniques. Dummy resist planarization uses the same method as resist planarization but also incorporates a resist mask as dummy active regions on the substrate to improve resist planarization. For reverse STI mask with wet or dry etch, a reverse mask is used to pattern the oxide, allowing the areas of the oxide over the active device regions to be subsequently etched using a wet or dry etch.
Each of these techniques reduces the non-planarity of the surface but is difficult to control. Therefore, a simple, less expensive, and more forgiving method of forming shallow-trench isolated bipolar structures, which minimizes over-polishing of small active device regions and provides for consistent oxide step height regardless of the size of the active device region, is desirable.
SUMMARY
The present invention provides improved dielectric polish control adjacent to device areas, compared to prior art STI processes. This is particularly important for bipolar structures, although the method may be used for MOS structures as well.
In an embodiment of the invention, dielectric polish control is improved by performing two STI polish steps using two polish stop layers rather than the single STI polish step and single polish stop layer of conventional processes. A trench isolation structure, for example, a shallow trench isolation structure, includes a multi-layer film stack on active device regions of a semiconductor substrate, where the multi-layer film stack includes at least two polish stop layers. Note that although the terms “trench isolation structure,” “shallow trench isolation,” and “STI” are used herein, in some embodiments devices are not electrically isolated from one another but rather are separated from one another. In an embodiment of the invention, the multi-film stack includes a second oxide layer deposited directly on the substrate, a second nitride polish stop layer deposited on the second oxide layer, a first oxide layer deposited on the second nitride polish stop layer, and a first nitride polish stop layer deposited on the first oxide layer.
The active device regions are separated by one or more trenches, which are etched through the multi-film stack and into corresponding underlying regions of the substrate. After the trenches are etched, a passivation thermal oxidation layer is grown on the etched surface. An oxide, which may be referred to as a trench oxide, is deposited to fill the trenches and to cover the top of the multi-film stack. The oxide serves to separate the active device regions of an integrated circuit from one another. Junctions that are shallower than the STI trench may be electrically isolated from one another by the trench oxide.
After the trench oxide is deposited, a first polish is performed. The first polish removes the trench oxide to the level of the first nitride polish stop layer. In an embodiment of the invention, the first polish is selective to nitride with respect to oxide. That is, the first polish removes oxide more readily than it removes nitride. According to an embodiment of the invention, the first polish is chemical mechanical polishing (CMP) using a highly selective cerium-based slurry.
The first nitride polish stop layer is removed after the first polish. In one embodiment, the first nitride polish stop layer is removed using a method that is selective to oxide with respect to nitride. That is, the method removes nitride more readily than it removes oxide. According to an embodiment of the invention, the first nitride polish stop layer is removed using a hot phosphoric acid etch, which is highly selective to oxide with respect to nitride.
A second polish is performed, which polishes the oxide to the level of the second nitride polish stop layer. The second polish is selective to nitride with respect to oxide. According to an embodiment of the invention, the second polish is chemical mechanical polishing (CMP) using a highly selective cerium-based slurry. The second nitride polish stop layer is removed after the second polish. In one embodiment, the second nitride polish stop layer is removed using a method that is selective to oxide with respect to nitride. For example, the second nitride polish stop layer may be removed using a hot phosphoric acid etch, which is highly selective to oxide with respect to nitride.
In an embodiment of the invention, a second oxide layer remains on the substrate after the second polish. Subsequent to the second polishing step, the oxide step height at the edge of the active device regions is approximately equal to the thickness of the second polish stop layer, regardless of the size of the active device region.

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