Multi-layer bus system having a bus control circuit

Details Multi-layer bus system having a bus control circuit Multi-layer bus system having a bus control circuit

2006-01-13

2008-05-13

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S110000, C710S306000, C710S317000

Reexamination Certificate

active

07373450

ABSTRACT:
A multi-layer bus system includes an interconnect matrix, bus slaves, bus masters and a bus control circuit. The interconnect matrix has master connection ports and slave connection ports, and connects one of the master connection ports to one of the slave connection ports in response a control signal. The slaves are connected to the slave connection ports, respectively. The bus masters includes a priority bus master connected to one of the master connection ports and a non-priority bus master. The priority bus master generates a bus demand signal when it needs a real-time operation. The bus control circuit is connected between the non-priority bus master and the other master connection ports. The bus control circuit disconnects the non-priority bus master to the other master connection ports in response to the bus demand signal.

REFERENCES:
patent: 5555543 (1996-09-01), Grohoski et al.
patent: 7219178 (2007-05-01), Harris et al.
patent: 2004/0123011 (2004-06-01), Murayama et al.
patent: 2005/0198429 (2005-09-01), Hoshi et al.
patent: 2005/0235084 (2005-10-01), Nariai
“Multi-layer AHB Overview”, DV10045B, May 2004, published by ARM, pp. 1-8.

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