Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-02-14
2006-02-14
Myers, Paul R. (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S052000
Reexamination Certificate
active
07000055
ABSTRACT:
A symmetric multiprocessor system includes a first processor and a second processor for executing a multi-threaded process on packets, a first inbound interface and a first outbound interface associated with the first processor, a first task queue accessible for reading by the first processor, a second inbound interface and a second outbound interface associated with the second processor, and a second task queue accessible for reading by at least the first processor. The first inbound interface receives incoming packets and has a first input buffer maintaining a first input queue of the packets for processing by the first processor. The first outbound interface receives packets from the first processor and transmits outgoing packets. The first task queue receives packets output from at least the second processor and maintains another input queue of the packets for processing by the first processor and which are outgoing from the first outbound interface. The second inbound interface receives incoming packets and has a second input buffer maintaining a second input queue of the packets. The second outbound interface receives packets from the second processor and transmits outgoing packets. The second task queue receives packets output from at least the first processor and maintains another input queue of the packets for processing by the second processor and which are outgoing from the second outbound interface. The first processor executes a process thread on packets by requesting the packets from the first input queue and the first task queue in a predetermined manner. The second processor executes a process thread on packets by requesting the packets from the second input queue and the second task queue in a predetermined manner.
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Kon Ronnie B.
Robins Kristen Marie
Cisco Technology Inc.
Myers Paul R.
Ritchie David B.
Thelen Reid & Priest LLP
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