Multi-instruction set flag preservation apparatus and method

Details Multi-instruction set flag preservation apparatus and method Multi-instruction set flag preservation apparatus and method

2005-06-07

2005-06-07

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Instruction modification based on condition

C712S227000, C712S228000, C703S026000

Reexamination Certificate

active

06904515

ABSTRACT:
A method and apparatus for processing program instructions, utilizes native fixed length instructions that include at least one flag modification enable bit. The flag modification enable bit is typically sent with the operation code and other information in the native instruction and is set to allow updating of one or more flags, such as stored in flag registers, associated with non-native instructions, such as variable length instructions. In addition, a flag modification enable bit may be set to preserve flag bit setting for variable length instructions that are emulated using the fixed length native instructions, to prevent overwriting of flag settings during emulation of variable length instructions.

REFERENCES:
patent: 5590359 (1996-12-01), Sharangpani
patent: 5832258 (1998-11-01), Kiuchi et al.
patent: 6173394 (2001-01-01), Guttag et al.
patent: 9713194 (1997-04-01), None

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