Multi-input semiconductor logic device with mask pattern for red

Details Multi-input semiconductor logic device with mask pattern for red Multi-input semiconductor logic device with mask pattern for red

1997-10-24

2000-07-04

Tokar, Michael

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

257393, 257401, H03K 1920, H01L 2976

Patent

active

060844361

ABSTRACT:
A multi-input semiconductor logic device capable of high-speed operation includes a first to fifth source/drain regions formed in an active area, and first to fourth gate electrodes formed over the active area through a gate insulating layer. The first to fifth source/drain regions are arranged along an axis of the active area. The second and fourth source/drain regions are located to be adjacent to the first source/drain region at each side of the first source/drain region. The third and fifth source/drain regions are located to be adjacent to the second and fourth source/drain regions, respectively. The first gate electrode is located between the first and second source/drain regions. The second gate electrode is located between the first and fourth source/drain regions. The third gate electrode is located between the second and third source/drain regions. The fourth gate electrode is located between the fourth and fifth source/drain regions. The first and fourth gate electrodes are electrically connected to be applied with a first digital input signal. The second and third gate electrodes are electrically connected to be applied with a second digital input signal. The third and fifth source/drain regions are electrically connected.

REFERENCES:
patent: 4494020 (1985-01-01), Konishi
patent: 4547681 (1985-10-01), Egawa
patent: 4716308 (1987-12-01), Matsuo et al.
patent: 5016077 (1991-05-01), Sato et al.

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