Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-28
2004-11-09
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S360000, C257S362000, C257S401000
Reexamination Certificate
active
06815776
ABSTRACT:
RELATED APPLICATION
The present application claims the benefit of Korean Patent Application No. 87295/2000 filed Dec. 30, 2000, under 35 U.S.C. § 113, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge protection circuit, and more particularly, to a multi-finger type electrostatic discharge protection circuit.
2. Background of the Related Art
Electrostatic discharge (ESD) characteristics Of a device generally depend an whether or not the MOS transistors of an ESD protection circuit properly allow the discharge of ESD pulses. A general ESD protection circuit has a multi-finger structure in which a plurality of gates are arranged consecutively in a single active area so as to discharge the ESD pulses.
FIG. 1
illustrates a layout of a multi-finger type ESD protection circuit according to a related art.
Referring to
FIG. 1
, in this multi-finger type ESD protection circuit having NMOS transistors, a plurality of gates (gate fingers)
103
are arranged in a large active region
100
side by side in a multi-finger configuration. A n+ type source region
101
and a n+ type drain region
102
are symmetrically arranged on both sides of each gate
103
to form NMOS type transistors. Contacts
104
and a p+ type active region
105
for bulk (substrate) bias are provided around the active region
100
.
Generally, the drain region
102
is connected to an input or output pad, and the source and active regions
101
and
105
are connected to a ground Vss. The gates
103
are also connected to the ground Vss. If the NMOS transistor is used as a pull-down transistor, the gate
103
is connected to an output of a pull-down inverter as known in the art.
The npn bipolar operation between an n+ junction of the source region
101
and the other n+ junction of the adjacent drain region
102
discharges, as known, a positive ESD pulse having been applied thereto through an input/output pad as a Vcc reference voltage. A negative ESD pulse having been applied thereto through an input/output pad as a Vcc reference voltage is discharged by the forward npn bipolar operation between an n+ junction of the drain region
102
and the p+ junction of the active region
105
.
FIG. 2
is a functional diagram of the ESD protection circuit having the multi-finger type NMOS transistors as shown in FIG.
1
.
As mentioned in the above explanation, in
FIG. 2
, if a Vcc reference voltage is applied to a particular input/output pad
11
connected to the drain regions, the corresponding NMOS transistor
10
discharges an ESD pulse by an npn bipolar operation between n+ junctions of the source and drain regions of the corresponding NMOS transistor
10
.
However, it may happen that portions of the gate fingers are not turned on in a conventional multi-finger type NMOS transistor structure when an ESD pulse is applied thereto. As a result, npn bipolar operations are not carried out uniformly in all the gate fingers. But, the parasitic npn bipolar operation occurs locally in some of the gate fingers. Thus, the other gate fingers fail to perform the parasitic npn bipolar operation. Such a phenomenon worsens as the number of multi-finger type transistors increases, whereby the ESD protection circuit according to the related art fails to carry out the ESD protection function as designed.
Further, a Vcc reference ESD pulse having been applied thereto through an input/output pad as a Vcc reference is discharged by a forward non bipolar operation between the n+ junction of the drain region and the p+ junction of the active region. Yet, all of the n+ junctions of the drain regions in the conventional multi-finger type NMOS transistor structures fail to have uniform resistance against the p+ junction of the active region, whereby the ESD pulse discharge performance of the ESD protection circuit according to the related art is weak and needs improvement.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a multi-finger type electrostatic discharge protection circuit/device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a multi-finger type electrostatic discharge protection circuit/device with improved ESD protection performance and characteristics.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a multi-finger type electrostatic discharge protection circuit according to an embodiment of the present invention includes a semiconductor substrate, a plurality of active regions formed separately on the semiconductor substrate, and a pair of gates formed on each of the respective active regions. Preferably, the present invention discharges an ESD pulse effectively by forming additional n+ (or p+) type active regions, which are connected to Vcc (or Vss), between the respective active regions.
In another aspect of the present invention, a multi-finger type electrostatic discharge protection circuit includes a semiconductor substrate, a plurality of active regions formed separately on the semiconductor substrate, a pair of gates formed on each of the respective active regions, and predetermined conductive type active regions formed between the respective active regions.
In a further aspect of the present invention, a multi-finger type electrostatic discharge protection circuit includes a semiconductor substrate, a plurality of active regions formed separately on the semiconductor substrate, a pair of gates formed on each of the respective active regions, drain regions formed at n+ junctions of both ends of the respective active regions, source regions formed between the two gates of the respective active regions, and predetermined conductive type active regions formed between the respective active regions.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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Lee Myoung Goo
Park Hong Bae
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Landau Matthew C
Thomas Tom
LandOfFree
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