Multi-FIFO integrated circuit devices that support...

Details Multi-FIFO integrated circuit devices that support... Multi-FIFO integrated circuit devices that support...

2006-10-10

2006-10-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S189011, C365S189020, C365S230050

Reexamination Certificate

active

07120075

ABSTRACT:
An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes. The multi-Q mode of operation supports write path queue switching that is free of write word fall-through and read path queue switching that is free of read word fall-through. The multi-Q mode also supports write path queue switching on every write cycle in both SDR and DDR write modes and independent read path queue switching on every read cycle in both SDR and DDR read modes.

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Invitation to Pay Additional Fees, Annex to Form PCT/ISA/206, Communication Relating to the Results of the Partial International Search, PCT/US02/26516, Oct. 13, 2003.

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