Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-30
2003-04-01
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06543034
ABSTRACT:
BACKGROUND
The present invention relates to electronic devices, and more particularly, but not exclusively, relates to the simulation and testing of integrated circuitry.
Simulation, laboratory testing, and production testing are typical stages encountered during integrated circuit development and manufacture. Unfortunately, there is often little or no commonality in the code and/or test devices used in these different stages. In one scheme, laboratory testing makes no use of the code used to simulate integrated circuit designs, and this code finds only limited use in production testers often at slower speeds than typically desired. This situation can lead to difficulties in isolating design, validation, and/or production problems. With the continued increase in circuit complexity, including, but not limited to the development of “System-on-Chip” (SoC) technology, these difficulties have generally become more significant.
Thus, there is a need for further contributions in this area of technology. The present invention addresses this need.
SUMMARY
One embodiment of the present invention is a unique technique for simulating and/or testing circuitry. Other embodiments of the present invention include unique devices, methods, systems, and apparatus to simulate and/or test integrated circuits.
A further embodiment of the present invention includes designing an integrated circuit that has a communication device and simulating operation of the communication device with a model of the integrated circuit and a model of a responder circuit. The integrated circuit and responder circuits are fabricated based on these models and the integrated circuit is tested with the responder circuit. The models may be defined by a Hardware Description Language (HDL) or with the “C” programming language to name a few examples.
In another embodiment of the present invention, a simulation is conducted with a system-on-chip integrated circuit model and a responder integrated circuit model. A system-on-chip integrated circuit corresponding to the system-on-chip integrated circuit model and a responder integrated circuit corresponding to the responder integrated circuit model are provided. The system-on-chip integrated circuit is tested with the responder integrated circuit.
In still another embodiment, a computer-readable device carries instructions executable to provide a simulation of a SoC integrated circuit with a first integrated circuit model and a responder integrated circuit with a second integrated circuit model. The first model defines the SoC integrated circuit to include one or more processors and one or more communication devices and the second model defines the responder integrated circuit to include at least one processor and several communication interfaces. The instructions are further executable to simulate operation of the one or more communication devices with the responder integrated circuit being in a slave mode responsive to commands from the SoC integrated circuit.
One object of the present invention is to provide a unique technique for simulating and/or testing circuitry.
Another object of the present invention is to provide a unique device, method, system, or apparatus to simulate and/or test integrated circuits.
Further objects, embodiments, forms, features, benefits, and advantages of the present invention shall become apparent from the description and figures included herewith.
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Goff Lonnie C.
Logsdon Brian D.
Petryk Edward M.
Koninklijke Philips Electronics , N.V.
Lin Sun James
Smith Matthew
Zawilski Peter
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