Multi-emitter BICMOS logic circuit family with superior performa

Details Multi-emitter BICMOS logic circuit family with superior performa Multi-emitter BICMOS logic circuit family with superior performa

1991-03-08

1992-11-24

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, H03K 1704

Patent

active

051665522

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates in general to BICMOS logic circuits (bipolar and CMOS circuitry on the same chip), and more particularly to a new family of logic circuits with improved power delay product while still maintaining the low power dissipation, high input impedance and the high noise immunity of the CMOS devices on the one hand, and the high drive capabilities of the bipolar devices on the other hand.
Several BICMOS circuits have been described in the literature. All of these circuits work on the same principle: bipolar transistors operate as a push-pull current booster, while Field Effect Transistors (NFET's and PFET's) are intended to constitute logic functions and to drive the base current of the bipolar transistors. In other words, in an optimized circuit designed to obtain the best use of both bipolar and unipolar technologies, FET's are used for logic implementation, and bipolar transistors for load driving.
Examples of such optimized circuits, are given in the following references:
Ref. 1: "How Motorola Moved BIMOS Up To The VLSI Levels," Electronics, Jul. 10, 1986, pp. 67-70.
Ref. 2: "CMOS/Bipolar Circuits for 60 MHz Digital Processing" by T. Hotta et al, IEEE Journal of SSC, Vol. SC-21 No. 5, October 1986, pp. 808-813.
Ref 3. "A Subnanosecond BI-CMOS Gate Array Family" by H. Nakashiba et al, IEEE 1986, Custom Integrated Circuits Conference, pp. 63-66.
FIGS. 1A and 1B of the present application depict two known BICMOS NAND gate circuits as published in references 1 and 2 respectively.
FIG. 1A shows a standard implementation of a two input BICMOS NAND gate circuit referenced 10, with FET and bipolar devices, as illustrated in FIG. 3 of Ref 1.
From FIG. 1A, it may be understood that the logic block Fp is built with PFET's P11 and P12. F.sub.P and Fn provide the base current to NPN transistors T11 and T12, respectively, when these transistors are turned on. T11 and T12 are the pull-up and pull-down transistors respectively of the gate circuit, and act as the driving devices for the next stages The common node between emitter of T11 and collector of T12 is the output node referenced OUT and is connected to the output terminal where the logic function F performed by the gate circuit is available.
To cut off T11, electric charges stored at the node UP must be evacuated. This discharge is controlled by the logic block F1 comprised of N13 and N14, similar to Fn. However, it is to be noted, that the discharge can also be done through a resistor (such as referenced Z in Ref. 3).
For the same reason, to cut off T12, node DN is discharged by a discharge device Z11 such as a feedback NFET, the gate of which is tied to the UP node (it might be connected to the OUT node as well). Node DN might also be discharged by a resistor (such as referenced Z in Ref 3).
The logical operation of the NAND gate circuit shown in FIG. 1A may be explained as follows
When input A or B (or both) is "low" (`0` logic), the node UP is set at the same voltage as Vdd by PFETs, T11 is turned on, while T12 is cut off because of the "off" state of the two NFETs, so that output OUT is set to "high" (`1` logic).
When inputs A and B are both "high", none of PFETs is conducting, T11 is off, while T12 is turned on by the NFETs Output OUT is set to "low".
Now, let input A (or B) go from "high" to "low", the other one staying "high", one of PFETs P11 (or P12) will turn on T11, while the T12 base is no longer biased into conduction because N11 (or N12) is set to the off state. Therefore, the output will go from "low" to "high". Accordingly the logic function f=A.multidot.B is available at output OUT.
FIG. 1B shows another embodiment of a two input BICMOS NAND gate circuit similar to the one shown in FIG. 2A of Ref. 2. The circuit of FIG. 1B referenced 11 has some similarities with circuit 10 of FIG. 1A. However, logic block F1 comprised of N17 and N18 is now connected to the ground instead of the DN node, and the discharge device Z12 is a resistor.
The capacitive load at the output node OUT is charged up or dis

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patent: 4703203 (1987-10-01), Gallup et al.

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