Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2011-06-14
2011-06-14
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C333S124000
Reexamination Certificate
active
07961003
ABSTRACT:
A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each of the line segments terminates at a drop point and each drop point is coupled to a load impedance. The characteristic impedance of a line segment is matched to the equivalent impedance presented by the load impedance in combination with the characteristic impedance of a following segment, or is matched to the load impedance if there is no following segment.
REFERENCES:
patent: 6067594 (2000-05-01), Perino et al.
patent: 2003/0065877 (2003-04-01), Gillingham et al.
Le Don P
Morgan & Lewis & Bockius, LLP
Rambus Inc.
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