Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2007-02-27
2007-02-27
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S034000, C710S036000
Reexamination Certificate
active
11124850
ABSTRACT:
Multi-dimensional data routing fabric simultaneously transfers multiple data packets between data processing components. Data packets are transported by arrays of data routing junctions dispersed along multiple routing dimensions. Data routing junctions are interconnected along each of routing dimensions with a mesh of data routing lines. Data transfers are accomplished by source components launching data packets into the multi-dimensional data routing fabric, and destination components receiving the routed data packets from the fabric. Each packet is guided by a chain of adjacent data routing junctions to converge on its destination. Individual data routing junctions along the packet's path make routing decisions by comparing the current location and direction of movement of the packet to the location of its destination. Based on the results of these comparisons, data packets are passed straight through to the next junction ahead, or are turned to an adjacent junction to the side of the current path.
REFERENCES:
patent: 4270169 (1981-05-01), Hunt
patent: 4805091 (1989-02-01), Thiel
patent: 4908751 (1990-03-01), Smith
patent: 4933836 (1990-06-01), Tulpule
patent: 5133073 (1992-07-01), Jackson
patent: 5170482 (1992-12-01), Shu
patent: 5255368 (1993-10-01), Barry
patent: 5341504 (1994-08-01), Mori
patent: 5345578 (1994-09-01), Manasse
patent: 5379440 (1995-01-01), Kelly
patent: 5430885 (1995-07-01), Kaneko
patent: 5430887 (1995-07-01), Hsiao
patent: 5598570 (1997-01-01), Ho
patent: 5642524 (1997-06-01), Keeling
patent: 5669008 (1997-09-01), Galles
patent: 5675823 (1997-10-01), Hsiao
patent: 5689722 (1997-11-01), Swarztrauber
patent: 5826033 (1998-10-01), Hayashi
patent: 5841775 (1998-11-01), Huang
patent: 5842031 (1998-11-01), Barker
patent: 5842034 (1998-11-01), Bolstad
patent: 6038688 (2000-03-01), Yoon
patent: 6230252 (2001-05-01), Passint
patent: 6240090 (2001-05-01), Enhager
patent: 6426952 (2002-07-01), Francis
patent: 2002/0018470 (2002-02-01), Galicki
patent: 2002/0018480 (2002-02-01), Galicki
patent: 2002/0027908 (2002-03-01), Kalkunte
patent: 2002/0027912 (2002-03-01), Galicki
patent: 2002/0085578 (2002-07-01), Dell
patent: 2002/0105972 (2002-08-01), Richter
McGregor, Interconnects Target SoC Design, Microprocessor Report, Jun. 28, 2004, In-Stat/MDR Publication, Reed Electronics Group, US.
Galicki, Multiprocessing I/O Enables Efficient 3G Base-Station Designs, EDN, Jul. 24, 2003, Reed Electronics Group, Highland Ranch CO.
Galicki, Connectivity Fabric Eases Base-Station Woes, Wireless Systems Design, Jun. 2003, Penton Technology Media, Paramus NJ.
Galicki, FPGAs Have the Multiprocessing I/O Infrastructure to Meet 3G Base Station Design Goals, Spring 2003, Xcell Journal, Xilinx, San Jose, CA.
Perveen Rehana
Rehman Mohammed H.
LandOfFree
Multi-dimensional data routing fabric does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-dimensional data routing fabric, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-dimensional data routing fabric will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3826827