Multi-die IC package and manufacturing method

Details Multi-die IC package and manufacturing method Multi-die IC package and manufacturing method

2005-09-09

2010-10-19

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S666000, C257S777000, C257S783000, C257SE25006, C257SE25013, C257SE25021, C257SE25027, C257SE23085

Reexamination Certificate

active

07816775

ABSTRACT:
A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second side opposite to the first side. A second die is attached onto the adhesive. The adhesive fills into the gaps defined by the set of leads. The adhesive is thereafter cured. In a multi-chip integrated circuit package made according to the method, the adhesive attaching the second die fills the gaps between the leads so that to avoid formation of internal cavities of the package.

REFERENCES:
patent: 5780925 (1998-07-01), Cipolla et al.
patent: 5812381 (1998-09-01), Shigeta et al.
patent: 6036173 (2000-03-01), Neu et al.
patent: 6072243 (2000-06-01), Nakanishi
patent: 6635138 (2003-10-01), Choi
patent: 7215008 (2007-05-01), Kim et al.

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