Multi-core multi-thread processor

Details Multi-core multi-thread processor Multi-core multi-thread processor

2007-04-24

2007-04-24

Peikari, B. James (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C711S119000, C710S306000, C710S317000, C710S052000

Reexamination Certificate

active

10272786

ABSTRACT:
In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.

REFERENCES:
patent: 5694573 (1997-12-01), Cheong et al.
patent: 5778243 (1998-07-01), Aipperspach et al.
patent: 5802576 (1998-09-01), Tzeng et al.
patent: 5895487 (1999-04-01), Boyd et al.
patent: 6088788 (2000-07-01), Borkenhagen et al.
patent: 6272520 (2001-08-01), Sharangpani et al.
patent: 6567839 (2003-05-01), Borkenhagen et al.
patent: 6938147 (2005-08-01), Joy et al.
patent: 0 747 816 (1996-12-01), None
Luiz Barroso et al., “Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing”, Proceedings of the 27th International Symposium on Computer Architecture 2000, pp. 282-293, 2000.
Keith Diefendorff, “Power4 Focuses on Memory Bandwidth”, Microprocessor Report, vol. 13, No. 13 (Oct. 6, 1999).
Joel M. Tendler et al., “IBM E-server POWER4 System Microarchitecture”, IBM Technical White Paper, Oct. 2001.
Pankaj Gupta, Nick McKeown, “Designing and Implementing A Fast Crossbar Scheduler”, 1999,IEEE.
IBM Corp., “Improved Store-Thru Cache”, IBM Technical Disclosure Bulletin, vol. 34, No. 1, Jun. 1991.

Affiliated with

Also associated with

Rating

Multi-core multi-thread processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-core multi-thread processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-core multi-thread processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3796147