Multi-core multi-thread processor

Details Multi-core multi-thread processor Multi-core multi-thread processor

2011-01-18

2011-01-18

Thai, Tuan V (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S120000, C711S122000, C711S138000, C710S305000, C710S306000, C710S317000, C710S052000, C712S032000, C712S034000

Reexamination Certificate

active

07873785

ABSTRACT:
A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.

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