Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-08-29
2006-08-29
Atrve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S056000, C710S315000, C370S402000
Reexamination Certificate
active
07099983
ABSTRACT:
A communications module for a data communications system having a plurality of data processors comprises a plurality of ports, each coupled to a respective one of the data processors. An address table associates addresses of a memory space to addresses of the data processors. The memory space may include addressable FIFOs, SRAM memory and/or flag registers. In the case of FIFOs, a counter coupled to the FIFO supplies a flag or ready signal indicating the not-full or not-empty status of the respective FIFO, which is supplied to a master device that is writing data to the FIFO or that is reading data from the FIFO so that the writing master device will write only when the FIFO is not full and the reading master device will read only when the FIFO is not empty.
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Emerson Steven M.
Hammitt Gregory F.
Kopacek Steven G.
Atrve Glenn A.
King Justin
LSI Logic Corporation
Westman Champlin & Kelly
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