Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2008-07-08
2008-07-08
Li, Aimee J (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S206000
Reexamination Certificate
active
10083872
ABSTRACT:
The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process “multi-threaded” instructions. Selectively, the architecture either (a) processes singly-threaded instructions through a single cluster to avoid bypassing and to increase throughput, or (b) processes singly-threaded instructions through multiple processes to increase “per thread” performance. The architecture may be “configurable” to operate in one of two modes: in a “wide” mode of operation, the processor's internal clusters collectively process bundled instructions of one thread of a program at the same time; in a “throughput” mode of operation, those clusters independently process instruction bundles of separate program threads. Clusters are often implemented on a common die, with a core and register file per cluster.
REFERENCES:
patent: 5303354 (1994-04-01), Higuchi et al.
patent: 5689677 (1997-11-01), MacMillan
patent: 5729761 (1998-03-01), Murata et al.
patent: 5903771 (1999-05-01), Sgro et al.
patent: 6098165 (2000-08-01), Panwar et al.
patent: 6151668 (2000-11-01), Pechanek et al.
patent: 6269437 (2001-07-01), Batten et al.
patent: 6272616 (2001-08-01), Fernando et al.
patent: 6446191 (2002-09-01), Pechanek et al.
patent: 6629232 (2003-09-01), Arora et al.
patent: 6954846 (2005-10-01), Leibholz et al.
patent: 2003/0033509 (2003-02-01), Leibholz et al.
patent: 2003/0093655 (2003-05-01), Gosior et al.
patent: 2003/0135711 (2003-07-01), Shoemaker et al.
patent: 2000-029731 (2000-01-01), None
patent: WO 9924903 (1999-05-01), None
InstantWeb. Free On-Line Dictionary of Computing (FOLDOC). http://www.instantweb.com/foldoc/foldoc.cgi?computer+dictionary search terms: latch and register.
InstantWeb. “Online Computing Dictionary”. © 1994-1999. Search Terms: VLIW; horizontal microcode; horizontal encoding; superscalar. http://www.instantweb.com/foldoc/foldoc.cgi?computer+dictionary.
Intel. “Hyper-Threading Technology”. Intel Technology Journal: vol. 06 Issue 01. © Feb. 14, 2002. pp. 1-66.
Heuring, Vincent P. and Jordan, Harry F. “Computer Systems Design and Architecture”. Reading, Mass.: Addison Wesley Longman, Inc., © 1997. pp. 151 and 534-535.
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