Multi chip package structure having a plurality of...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices

Reexamination Certificate

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Reexamination Certificate

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06972487

ABSTRACT:
The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor Substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second Semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.

REFERENCES:
patent: 5640107 (1997-06-01), Kruse
patent: 5754405 (1998-05-01), Derouiche
patent: 5949139 (1999-09-01), Imura et al.
patent: 6043539 (2000-03-01), Sugasawara
patent: 6081429 (2000-06-01), Barrett
patent: 6116493 (2000-09-01), Tanaka
patent: 6125069 (2000-09-01), Aoki
patent: 6157213 (2000-12-01), Voogel
patent: 6208018 (2001-03-01), Ma et al.
patent: 6359340 (2002-03-01), Lin et al.
patent: 6362651 (2002-03-01), Voogel
patent: 6365966 (2002-04-01), Chen et al.
patent: 6392304 (2002-05-01), Butler
patent: 6407456 (2002-06-01), Ball
patent: 6580164 (2003-06-01), Ohie
patent: 2002/0135055 (2002-09-01), Cho et al.
patent: 0 907 207 (1999-06-01), None
patent: 62136844 (1987-06-01), None
patent: 2-122559 (1990-05-01), None
patent: 4-7867 (1992-01-01), None
patent: 6-177321 (1994-06-01), None
patent: 07-94617 (1995-04-01), None
patent: 8-222514 (1996-08-01), None
patent: 9-219419 (1997-08-01), None
patent: 10-144862 (1998-05-01), None
patent: 10-321742 (1998-12-01), None
patent: 11-74464 (1999-01-01), None
patent: 11-31781 (1999-02-01), None
patent: 11-145403 (1999-05-01), None
patent: 11-168185 (1999-06-01), None
patent: 11-330256 (1999-11-01), None
patent: 11-354714 (1999-12-01), None
patent: 2000-223651 (2000-08-01), None
patent: WO 99/60618 (1999-11-01), None
Langenkamp et al., “A Low-Cost MCM Implementation for 100-Hz TV Up-conversion”, Apr. 1998, Multichip Modules and High Density Packaging, 7th International Conference, pp. 537-542.
Gross et al., “ESD Qualification and Testing of Semiconductor Electronic Components”, May 1996, Electronic Components and Technology Conference, 46th, pp. 671-681.
Warner, Integrated Circuits Design Priciples and Fabrication, 1965, McGraw-Hill Book Company, 334-338.

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