Multi-chip package structure

Details Multi-chip package structure Multi-chip package structure

2007-11-06

2007-11-06

Williams, Alexander Oscar (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257SE25002, C257SE25013, C257SE25012, C257SE23069, C257SE23177, C257SE23178, C257SE25023, C257S686000, C257S685000, C257S723000, C257S724000, C257S728000, C257S737000, C257S738000, C257S698000, C257S789000, C257S780000, C257S684000, C257S790000, C257S787000, C257S786000, C257S784000, C257S778000

Reexamination Certificate

active

11353678

ABSTRACT:
The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

REFERENCES:
patent: 6521881 (2003-02-01), Tu et al.
patent: 6583512 (2003-06-01), Nakaoka et al.
patent: 6607937 (2003-08-01), Corisis
patent: 6677672 (2004-01-01), Knapp et al.
patent: 6700178 (2004-03-01), Chen et al.
patent: 6753599 (2004-06-01), Kim
patent: 6762488 (2004-07-01), Maeda et al.
patent: 7064426 (2006-06-01), Karnezos
patent: 7129583 (2006-10-01), Tao et al.
patent: 2004/0051212 (2004-03-01), Marcos
patent: 2004/0051213 (2004-03-01), Marcos
patent: 2004/0056277 (2004-03-01), Marcos
patent: 2004/0063242 (2004-04-01), Marcos
patent: 2004/0063246 (2004-04-01), Marcos
patent: 2004/0065963 (2004-04-01), Marcos
patent: 2004/0113253 (2004-06-01), Karnezos
patent: 2004/0113254 (2004-06-01), Karnezos
patent: 2004/0113255 (2004-06-01), Karnezos
patent: 2004/0113275 (2004-06-01), Karnezos
patent: 2004/0119152 (2004-06-01), Karnezos
patent: 2004/0119153 (2004-06-01), Karnezos
patent: 2004/0124518 (2004-07-01), Marcos
patent: 2005/0133916 (2005-06-01), Karnezos
“Electronic Packaging and Interconnection Handbook,” Third Edition, McGraw-Hill, p. 7.80.
“Microchip Fabrication,” Fourth Edition, McGraw-Hill, p. 542.

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