Multi-chip package for reducing parasitic load of pin

Details Multi-chip package for reducing parasitic load of pin Multi-chip package for reducing parasitic load of pin

2011-01-11

2011-01-11

Sefer, A. (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S723000, C257S786000, C257SE25006, C257SE25007, C438S110000, C438S129000

Reexamination Certificate

active

07868438

ABSTRACT:
Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

REFERENCES:
patent: 6621155 (2003-09-01), Perino et al.
patent: 2002/0074637 (2002-06-01), McFarland
patent: 2002/0096784 (2002-07-01), Kamikuri et al.
patent: 2003/0015733 (2003-01-01), Hayashi et al.
patent: 2003/0028835 (2003-02-01), Ishikawa
patent: 2003/0234674 (2003-12-01), Morgan

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