Multi-chip package and method for manufacturing the same

Details Multi-chip package and method for manufacturing the same Multi-chip package and method for manufacturing the same

2005-11-29

2005-11-29

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S686000, C257S723000, C361S735000, C361S749000

Reexamination Certificate

active

06969906

ABSTRACT:
Disclosed are a multi-chip package and a method for manufacturing the multi-chip package. The multi-chip package comprises: a circuit substrate consisting of first, second and third areas which surround three sides of the multi-chip package; and at least two semiconductor chips which are positioned within an internal space of the package defined by the internal surfaces of the above three areas, wherein the semiconductor chips are physically bonded and electrically connected to each other. The method for manufacturing a multi-chip package comprises the steps of: providing a circuit substrate matrix formed with a plurality of unit circuit substrates, each substrate consisting of first, second and third areas; bonding semiconductor chips each unit circuit substrate, so that those chips are physically bonded and electrically connected to the unit circuit substrate; separating unit circuit substrates from the circuit substrate matrix; and folding the unit circuit substrate.

REFERENCES:
patent: 6208521 (2001-03-01), Nakatsuka
patent: 6218214 (2001-04-01), Panchou et al.
patent: 6486544 (2002-11-01), Hashimoto
patent: 6699730 (2004-03-01), Kim et al.
patent: 2003/0062614 (2003-04-01), Larson

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