Multi-chip package

Details Multi-chip package Multi-chip package

2007-09-18

2010-02-23

Loke, Steven (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C438S107000

Reexamination Certificate

active

07667303

ABSTRACT:
A multi-chip package including a carrier, a first chip, a second chip and a first conductive layer is provided. The first chip is disposed on the carrier and is electrically connected to the carrier through at least one first wire. The second chip is disposed on the first chip and is electrically connected to the first chip through at least one second wire. The first conductive layer is disposed on the second chip and is electrically connected to the first chip or the second chip through at least one third wire. The first conductive layer is electrically connected to the carrier through the at least one fourth wire.

REFERENCES:
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5552966 (1996-09-01), Nagano
patent: 6215182 (2001-04-01), Ozawa et al.
patent: 6682954 (2004-01-01), Ma et al.
patent: 6897555 (2005-05-01), Lim et al.
patent: 7009303 (2006-03-01), Kuroda et al.
patent: 7214326 (2007-05-01), Yang et al.
patent: 2004/0150084 (2004-08-01), Nishida et al.
patent: 2005/0093167 (2005-05-01), Saeki
patent: 2005/0248019 (2005-11-01), Chao et al.

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