Multi-chip package

Details Multi-chip package Multi-chip package

1999-04-14

2000-07-11

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

257669, 257686, 257692, 257724, 257777, 257783, H01L 2348

Patent

active

060877227

ABSTRACT:
A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upper chip is bonded to the top surface of a lower chip. To stabilize the chips, auxiliary or inner leads of a lead frame attach to the top surface of a lower chip. This shortens wire lengths between the chips and the inner leads. The shorter wires reduce wire loop heights and thus reduce the probability of exposing wires in a subsequent transfer-molding. A multi-chip stack package which includes an auxiliary lead(s) is also disclosed. The auxiliary leads attach to the top surface of the lower chip and can provide a stable support of a semiconductor chip and prevent the chip from tilting and shifting in transfer-molding. An auxiliary lead can be between the lower and upper chips. The auxiliary leads can also be positioned to prevent undesirable spreading of an adhesive when an upper chip is attached to a lower chip.

REFERENCES:
patent: 5291061 (1994-03-01), Ball
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5463253 (1995-10-01), Waki et al.
patent: 5530292 (1996-06-01), Waki et al.
patent: 5640044 (1997-06-01), Takehashi et al.
patent: 5737191 (1998-04-01), Horiuchi et al.
patent: 5739581 (1998-04-01), Chillara et al.
patent: 5814881 (1998-09-01), Alagratnam et al.

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