Multi-chip module with extension

Details Multi-chip module with extension Multi-chip module with extension

2001-08-29

2003-09-16

Potter, Roy (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S613000

Reexamination Certificate

active

06620648

ABSTRACT:

BACKGROUND
This invention relates generally to multi-chip modules for coupling more than one chip together in a single package.
For a number of reasons, it is desirable to package more than one integrated circuit die or chip in a single package. In some cases, the two dice may necessitate different processing technologies. In such case, the two dice must be made independently and then combined thereafter. For example, one die may be made using a bipolar process and another may be made using a complementary metal oxide semiconductor (CMOS) process. Similarly, one die may use a logic process and the other die may use a memory process. For example, some dice may use stacked gate designs which may be incompatible with logic processes.
Thus, in a variety of situations, it may be desirable to put components in close proximity without making them on the same integrated circuit fabrication process. In addition, in some cases, the level of integration available may be such that to achieve the full capabilities, separate dice must be used. If separate dice are used, it may still be desirable to connect the dice together to the outside world through a single set of input and output connections. These input and output connections may be, for example, pins or solder balls. In some cases it may be desirable to interconnect the two dice to each other and then to interconnect them together to the outside world.
Thus, there is a need for packages which enable dice to be connected together before connection to the outside world.
SUMMARY
In accordance with one aspect, a multi-chip module includes a laminate layer having a top and a bottom sides and a passage. A first chip is secured to the bottom side of the layer. The first chip is wire bonded to the top side of the layer through the passage. A second chip is secured to the top side of the layer by bumps. The layer includes an extension accessible beyond one of the chips. The extension includes contacts on said bottom side, electrically coupled to said first and second chips.
Other aspects are described in the accompanying specification and claims.


REFERENCES:
patent: 5239198 (1993-08-01), Lin et al.
patent: 5696031 (1997-12-01), Wark
patent: 5917242 (1999-06-01), Ball

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